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- PhD or Master’s degree in microelectronics or electronics engineering.
- Solid understanding of digital ASIC design fundamentals, RTL design, EDA design tools (Cadence or Synopsys) and methodologies.
- Proven track record of RTL design, verification, synthesis, and timing analysis of complex digital systems (e.g., DFT, BUS Communication protocol).
- Experience in FPGA implementation, SoC IP integration, and RTL design for performance, low power, and low area.
- Knowledge of digital physical design (synthesis, scan, P&R, timing, reliability analysis, IR drop analysis, physical verification) is a strong plus.
- Experience in processor (ARM or RISC-V) implementation is a plus.
- Good communication skills in English.
- Conduct technical feasibility study, and define chip architecture and specifications
- Design and RTL programming of key building blocks
- Digital mixed-signal design support for PLL, ADC, DAC and other mixed-signal chips
- System-on-chip integration and verification
- Develop low-power machine learning processor chips
- Support lab evaluation phase
- Working on exciting projects and products development for world changing applications, such as deep-space planetary exploration, robot intelligence, and fusion energy production
- Opportunities to learn efficiently and quickly in a startup company with high growth potential
- Working in a very dynamic team with colleagues sharing the same vision on the company’s mission
- Competitive salary and social benefits
- Location: Mixed on-site (Geel/Leuven, Belgium) and home working
- Duration: Unlimited